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| author | Peter De Schrijver <[email protected]> | 2013-11-18 16:11:38 +0100 |
|---|---|---|
| committer | Peter De Schrijver <[email protected]> | 2013-11-26 18:46:53 +0200 |
| commit | b29f9e926442c35bd42ebd283aaed0de2c4f1477 (patch) | |
| tree | 478f053f15bf821bb82c7d8bc58ea1c861338082 /tools/perf/scripts/python/syscall-counts.py | |
| parent | bc44275b8ea2df7c77658b08955ec545a37560ab (diff) | |
clk: tegra: add TEGRA_PERIPH_NO_GATE
Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: Peter De Schrijver <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions