diff options
| author | Ritesh Harjani <riteshh@codeaurora.org> | 2016-11-21 12:07:21 +0530 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2016-11-29 09:05:17 +0100 |
| commit | b12d44db4b0187f536c487713ef39a22da990635 (patch) | |
| tree | 8cc3c51f4d367633fe1a3fc80d8630e5f961d73f /tools/perf/scripts/python/syscall-counts.py | |
| parent | edc609fd19e1cd1b6d0125915195a28c107a293b (diff) | |
mmc: sdhci-msm: Add clock changes for DDR mode.
SDHC MSM controller need 2x clock for MCLK at GCC.
Hence make required changes to have 2x clock for
DDR timing modes.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions