diff options
| author | Maxime Ripard <[email protected]> | 2020-09-03 10:01:03 +0200 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2020-09-07 18:04:17 +0200 |
| commit | 9e30cfd0764e1018897b8f4830d1cffd59a3fe40 (patch) | |
| tree | 5d94f4705750f943c84151716124780137116422 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 0d2b96af53c973942c8c5a2c6629915774bae187 (diff) | |
drm/vc4: crtc: Clear the PixelValve FIFO during configuration
Even though it's not really clear why we need to flush the PV FIFO during
the configuration even though we started by flushing it, experience shows
that without it we get a stale pixel stuck in the FIFO between the HVS and
the PV.
Signed-off-by: Maxime Ripard <[email protected]>
Tested-by: Chanwoo Choi <[email protected]>
Tested-by: Hoegeun Kwon <[email protected]>
Tested-by: Stefan Wahren <[email protected]>
Reviewed-by: Dave Stevenson <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/ccd6269ba37b2f849ba6e62471c99bd93a4548a0.1599120059.git-series.maxime@cerno.tech
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions