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authorHenry Chen <[email protected]>2016-01-04 20:02:52 +0800
committerMatthias Brugger <[email protected]>2016-01-25 18:59:41 +0100
commit73efe5792bfa73589a7e04abf773f8b7a4c01650 (patch)
treeb751f509e291a7f84a4235af95cdbb9fa6b50dc4 /tools/perf/scripts/python/syscall-counts.py
parent92e963f50fc74041b5e9e744c330dca48e04f08d (diff)
soc: mediatek: PMIC wrap: Clear the vldclr if state machine stay on FSM_VLDCLR state.
Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout, because pmic wrap is waiting for FSM_VLDCLR after finishing WACS2_CMD. It just return error when issue happened, so the state machine will stay on FSM_VLDCLR state when data send back later by PMIC and timeout again in next time because pmic wrap waiting for FSM_IDLE state at the beginning of the read/write function. Clear the vldclr when timeout if state machine stay on FSM_VLDCLR. Signed-off-by: Henry Chen <[email protected]> Tested-by: Ricky Liang <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
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