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author | Ville Syrjälä <[email protected]> | 2014-11-21 21:54:25 +0200 |
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committer | Daniel Vetter <[email protected]> | 2014-12-03 09:29:36 +0100 |
commit | 73bbf6bd907906dcbdc78f3af38a722c0fe498d8 (patch) | |
tree | e212bcbf12131ac43b021095701135ad0e2320ec /tools/perf/scripts/python/syscall-counts.py | |
parent | aaecdf611a05cac26a94713bad25297e60225c29 (diff) |
drm/i915: Fix gen4 GPU reset
On pre-ctg the reset bit directly controls the reset signal. We must
assert it for >=20usec and then deassert it. Bit 1 is a RO status bit
which should also go down when the reset is no longer asserted.
Tested-by: Kenneth Graunke <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions