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| author | Cong Dang <cong.dang.xn@renesas.com> | 2024-02-01 13:21:55 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-06 11:20:02 +0100 |
| commit | 6e8b1dcb0956668e77cc9177b810b7c1f15c6d8d (patch) | |
| tree | a5d44a08cf0fba19089c3ed6826f76b4f82664bf /tools/perf/scripts/python/syscall-counts.py | |
| parent | 62527c9d46a151163525482301cf79fecd5402ef (diff) | |
clk: renesas: r8a779h0: Add watchdog clock
Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f1dbf0f3f484015f2e629d78b746cf377d6f6746.1706790015.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions