diff options
| author | Théo Lebrun <[email protected]> | 2024-11-06 17:03:53 +0100 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2024-11-14 14:52:26 -0800 |
| commit | 6a46b75a91a4347e50b25fb4a150a8f34b026034 (patch) | |
| tree | 344e20865a63f3f6699b471df04734140280f386 /tools/perf/scripts/python/syscall-counts.py | |
| parent | a370b2d22dc0a68631fadca5080cd78fa99e4284 (diff) | |
dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
Add #defines for Mobileye clock controller:
- EyeQ5 core 0 thru 3 clocks. Internally:
EQ5C_PLL_CPU: already exposed
└── EQ5C_CPU_OCC: unexposed, no reason to do so
├── EQ5C_CPU_CORE0: new!
├── EQ5C_CPU_CORE1: new!
├── EQ5C_CPU_CORE2: new!
└── EQ5C_CPU_CORE3: new!
- EyeQ5 peripheral clocks. Internally:
EQ5C_PLL_PER: already exposed
├── EQ5C_PER_OCC: new!
│ ├── EQ5C_PER_SPI: new!
│ ├── EQ5C_PER_I2C: new!
│ ├── EQ5C_PER_GPIO: new!
│ └── EQ5C_PER_UART: new!
├── EQ5C_PER_EMMC: new!
└── EQ5C_PER_OCC_PCI: new!
- EyeQ6H central OLB. Internally:
EQ6HC_CENTRAL_PLL_CPU: new!
└── EQ6HC_CENTRAL_CPU_OCC: new!
- EyeQ6H west OLB. Internally:
EQ6HC_WEST_PLL_PER: new!
└── EQ6HC_WEST_PER_OCC: new!
└── EQ6HC_WEST_PER_UART: new!
Signed-off-by: Théo Lebrun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions