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authorNicolin Chen <[email protected]>2020-09-17 04:31:55 -0700
committerJoerg Roedel <[email protected]>2020-09-18 11:07:07 +0200
commit675d12acb66bb190d32a3fae187e379f01cbd8ce (patch)
treebfa799b0d6499d932ca5bc68dc04f75c5b553ea7 /tools/perf/scripts/python/syscall-counts.py
parentd5c152c3409ac1982a9277d8d344e073eda17e78 (diff)
memory: tegra: Correct num_tlb_lines for tegra210
According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines should be 48 (0x30) rather than 32 (0x20). Signed-off-by: Nicolin Chen <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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