diff options
| author | Tomer Tayar <[email protected]> | 2017-04-06 15:58:30 +0300 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2017-04-06 14:26:31 -0700 |
| commit | 60afed72f51c7445aa06dc953b05f5672b607860 (patch) | |
| tree | 01739ed7b696f08f2d03d388030516b1e55e22ed /tools/perf/scripts/python/syscall-counts.py | |
| parent | 1558296251207bb0def2ae7cc045f8159ee0c204 (diff) | |
qed: Configure cacheline size in HW
Default HW configuration is optimal for an architecture where cache
line size is 64B.
During chip initialization, properly initialize the cache line size
in HW to avoid possible redundant PCI transactions.
Signed-off-by: Tomer Tayar <[email protected]>
Signed-off-by: Yuval Mintz <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions