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authorSamuel Holland <[email protected]>2021-09-02 17:57:48 -0500
committerWim Van Sebroeck <[email protected]>2021-10-26 21:31:07 +0200
commit55f36df9ec4f6c53b6a06acfc4195e99bd9355fa (patch)
tree68cf67a3ce0c4f5cdac0558b512bea1f209a2aea /tools/perf/scripts/python/syscall-counts.py
parentf01f0717928a7d38615c8ef5a72217bd63677e5b (diff)
dt-bindings: watchdog: sunxi: Add compatibles for R329
On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) divided by 750. However, starting with R329, LOSC (OSC32k) is added as an alternative clock source, with a bit to switch between them. Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the cycle counts to keep the timeouts independent of the clock source. This keeps the programming interface backward-compatible. Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The first of these adds two more new registers, to allow software to immediately assert the SoC reset signal. Add an additional "-reset" suffix to signify the presence of this feature. Signed-off-by: Samuel Holland <[email protected]> Acked-by: Maxime Ripard <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Guenter Roeck <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Guenter Roeck <[email protected]> Signed-off-by: Wim Van Sebroeck <[email protected]>
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