diff options
| author | Ander Conselvan de Oliveira <[email protected]> | 2016-12-02 10:23:52 +0200 |
|---|---|---|
| committer | Ander Conselvan de Oliveira <[email protected]> | 2016-12-02 16:41:35 +0200 |
| commit | 51b3ee35affa3695bd89f6c6cdb22cd65aff5155 (patch) | |
| tree | 2aba0aa37accc8309a4743ec932feac8a1463ed0 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 0a116ce895e7ee2831c6304df246c40a33bcf454 (diff) | |
drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
Follow the PLL enable sequence updated in bspec, which requires the DCC
delay range 2 bit to be set.
v2: Moved from DDI init sequence to PLL enable.
v3: Don't read value from GRP register. (Rodrido)
Cc: Rodrigo Vivi <[email protected]>
Signed-off-by: Ander Conselvan De Oliveira <[email protected]>
Reviewed-by: Rodrigo Vivi <[email protected]>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-5-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions