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authorAndrzej Hajda <[email protected]>2016-03-23 14:15:12 +0100
committerInki Dae <[email protected]>2016-04-30 01:03:54 +0900
commit4677f51ade432987f01062abad9e4cf60fd33f7d (patch)
tree69e4da85beda6745dab2033fb23790e504a7edd6 /tools/perf/scripts/python/syscall-counts.py
parent50ec220eb4e3c90b3d7d40c679e19a0b61de162c (diff)
drm/exynos/hdmi: fix PHY configuration sequence
Proper PHY configuration should be as follow: 1. set HDMI clock parents to OSCCLK. 2. reconfigure PHY. 3. set HDMI clock parents to PHY. 4. wait for PLL stabilization. The patch fixes it and consolidates the code. Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Inki Dae <[email protected]>
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