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authorErwan Le Ray <[email protected]>2021-03-04 17:23:07 +0100
committerGreg Kroah-Hartman <[email protected]>2021-03-10 09:34:11 +0100
commit3db1d52466dc11dca4e47ef12a6e6e97f846af62 (patch)
tree4d69aad6139f71ecdb50c81e71d8c3ba41bdde84 /tools/perf/scripts/python/syscall-counts.py
parent9f77d19207a0e8ba814c8ceb22e90ce7cb2aef64 (diff)
serial: stm32: fix tx_empty condition
In "tx_empty", we should poll TC bit in both DMA and PIO modes (instead of TXE) to check transmission data register has been transmitted independently of the FIFO mode. TC indicates that both transmit register and shift register are empty. When shift register is empty, tx_empty should return TIOCSER_TEMT instead of TC value. Cleans the USART_CR_TC TCCF register define (transmission complete clear flag) as it is duplicate of USART_ICR_TCCF. Fixes: 48a6092fb41f ("serial: stm32-usart: Add STM32 USART Driver") Signed-off-by: Erwan Le Ray <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
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