diff options
| author | Peng Fan <[email protected]> | 2016-05-03 21:50:30 +0800 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2016-05-03 18:23:04 +0100 |
| commit | 3ca3712a42f9e632eb41da94ca4eab4f1fb06fcb (patch) | |
| tree | 091456c97c6d9c926df6bf5bf6800a59533f9c35 /tools/perf/scripts/python/syscall-counts.py | |
| parent | b7862e3559f9ab4aaa258dcb846986601a7ca0b8 (diff) | |
iommu/arm-smmu: Clear cache lock bit of ACR
According MMU-500r2 TRM, section 3.7.1 Auxiliary Control registers,
You can modify ACTLR only when the ACR.CACHE_LOCK bit is 0.
So before clearing ARM_MMU500_ACTLR_CPRE of each context bank,
need clear CACHE_LOCK bit of ACR register first.
Since CACHE_LOCK bit is only present in MMU-500r2 onwards,
need to check the major number of IDR7.
Reviewed-by: Robin Murphy <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions