diff options
| author | Peter Ujfalusi <[email protected]> | 2010-05-26 11:38:19 +0300 |
|---|---|---|
| committer | Liam Girdwood <[email protected]> | 2010-05-31 11:08:58 +0100 |
| commit | 3c36cc688e7ad4ab595a0ac59697e4e1d06338c5 (patch) | |
| tree | 622be36180386dbad7f19f169cf279249a19c427 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 9fdcc0f72af8801d8429a465a159d815774dbf6d (diff) | |
ASoC: TWL4030: Correct the ARXR2_APGA_CTL chip default
It seams at least on twl5031 that the ARXR2_APGA_CTL register
does not have the same default value as it is written in
the TRM.
Since the codec part of the PM chip has not been actually
changed according to TI, assuming, that all version has
the same problem, so writing there the TRM value.
Signed-off-by: Peter Ujfalusi <[email protected]>
Acked-by: Mark Brown <[email protected]>
Signed-off-by: Liam Girdwood <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions