diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-11-28 13:51:35 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-12-13 20:50:09 +0200 |
| commit | 273361f54e5bcaccdd725a9ffac14a9fac672451 (patch) | |
| tree | 73de96bb4956f14429045d14e3d8bb48baa9ea29 /tools/perf/scripts/python/syscall-counts.py | |
| parent | f23fe4d7d794c6d71dc6b8fdc510da2fc2174369 (diff) | |
drm/i915/mtl: Fix voltage_level for cdclk==480MHz
Allow MTL to use voltage level 1 for 480MHz cdclk,
instead of the voltage level 2 that it's currently using.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231128115138.13238-6-ville.syrjala@linux.intel.com
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions