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authorPaul Hsieh <[email protected]>2023-02-10 12:00:16 +0800
committerAlex Deucher <[email protected]>2023-02-28 14:30:55 -0500
commit26a9f53198c955b15161da48cdb51041a38d5325 (patch)
tree9203bb7454bf89b9baa9f17c924cbcacb9bfc94b /tools/perf/scripts/python/syscall-counts.py
parente68d1e074d5e94b609de01a3ad3287d3d17721f2 (diff)
drm/amd/display: Correct DML calculation to align HW formula
[Why] In 2560x1440@240p eDP panel, some use cases will enable MPC combine with RGB MPO then underflow happened. This case is not allowed from HW formula.  [How] Correct eDP, DP and DP2 output bpp calculation to align HW formula. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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