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| author | James Liao <[email protected]> | 2015-07-10 16:39:33 +0800 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2015-07-28 11:58:54 -0700 |
| commit | 196de71a9d9e9090406a87362d22b67ae633fa7a (patch) | |
| tree | 615be1dddf4c657e5114458cfae75d5e4e6ad6d7 /tools/perf/scripts/python/syscall-counts.py | |
| parent | b3be457e5854e3095cd0be850058c765aaf467ab (diff) | |
clk: mediatek: Fix calculation of PLL rate settings
Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).
Signed-off-by: James Liao <[email protected]>
Acked-by: Sascha Hauer <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions