diff options
| author | Lad Prabhakar <[email protected]> | 2021-06-09 16:32:28 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2021-06-10 15:46:46 +0200 |
| commit | 17f0ff3d49ff1a9d4027f9c2bef4725ab41aa9a5 (patch) | |
| tree | 888ed51b675da2a5fef45bf8bd94e7f7ad1f9daf /tools/perf/scripts/python/syscall-counts.py | |
| parent | 9c094430b9a6478b9a36b747d98331c03e08e623 (diff) | |
clk: renesas: Add support for R9A07G044 SoC
Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.
Based on a patch in the BSP by Binh Nguyen
<[email protected]>.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions