diff options
| author | Lendacky, Thomas <[email protected]> | 2014-07-29 08:57:37 -0500 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2014-07-30 18:46:53 -0700 |
| commit | 169a6303b89a99c807328f6f9772a81605b17116 (patch) | |
| tree | ad517fe0043d5ed6e3f0db706bda004411a40736 /tools/perf/scripts/python/syscall-counts.py | |
| parent | 853eb16b8b6a347315443f2ef010e5b97d8c1577 (diff) | |
amd-xgbe-phy: Updates to rate change complete check
Currently, the logic will loop endlessly waiting for a rate change
to complete. Add a counter so that if the rate change signals
never indicate complete the loop will eventually exit.
Signed-off-by: Tom Lendacky <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions