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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-30 10:47:49 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-31 11:19:24 +0100 |
| commit | 096311157d2a6bb8f06e28e1143e2a5de6a0183b (patch) | |
| tree | dd64bfa951a9d451926c2363bb3a233b1cc450b8 /tools/perf/scripts/python/syscall-counts.py | |
| parent | f077cab34df3010df6f4996e648dba5f43fd6b85 (diff) | |
clk: renesas: r8a779g0: Fix PCIe clock name
Fix a typo in the name of the module clock for the second PCIe channel.
Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions