diff options
| author | Andrzej Hajda <a.hajda@samsung.com> | 2015-03-18 02:14:07 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene@kernel.org> | 2015-03-18 02:14:07 +0900 |
| commit | ffb8b1ee9a704229f0b6753970ae09dc4d6863d9 (patch) | |
| tree | 4b7ef78e6f17436882be8e16cc30964a79c9e879 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 472c95a6e352413af068b42ab0db2b2e23c20756 (diff) | |
ARM: dts: add async-bridge clocks to disp1 power domain for exynos5420
FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions