diff options
| author | Gerhard Engleder <[email protected]> | 2022-09-27 21:58:37 +0200 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2022-09-30 11:31:34 +0100 |
| commit | ff46c610abd62a3dc120dc05ad726b2a47d347ea (patch) | |
| tree | 3601476e89eae72fb67be46741d02dd687e47944 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | d742ea6b8e85f7b0d484bc23392d607b50667da6 (diff) | |
dt-bindings: net: tsnep: Allow dma-coherent
Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.
Add "dma-coherent" property to allow the configuration of cache coherent
DMA.
Signed-off-by: Gerhard Engleder <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions