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authorLoic Poulain <[email protected]>2020-11-26 16:06:41 +0100
committerManivannan Sadhasivam <[email protected]>2021-01-21 13:05:53 +0530
commitf49b6aeb5c45dea3a1b6ee6a842599147dfd5929 (patch)
tree5b4991575ae1180a241988ff51f7062d2512947c /tools/perf/scripts/python/syscall-counts-by-pid.py
parentec751369d6fbc9f84176e1530b11cbf387262b48 (diff)
bus: mhi: Ensure correct ring update ordering with memory barrier
The ring element data, though being part of coherent memory, still need to be performed before updating the ring context to point to this new element. That can be guaranteed with a memory barrier (dma_wmb). Signed-off-by: Loic Poulain <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
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