diff options
| author | Swapnil Jakhade <[email protected]> | 2021-03-04 07:08:13 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2021-03-30 23:34:13 +0530 |
| commit | e25c9dbcfc17bfe4fb0b72cdb6926db708f1ed6b (patch) | |
| tree | 492b6eebc8315d6b4fd4e07aeafe5b9422537dcc /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 2cca0228f3641e68ac2433a8e75b130d907ce78a (diff) | |
phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clock
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was
expecting 10GHz clock, configuration was giving 8GHz clock. Update
register sequences to get correct PLL1 configuration.
Also, update single link PCIe and single link SGMII/QSGMII configurations
with related changes.
Signed-off-by: Swapnil Jakhade <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions