diff options
| author | Nikita Yushchenko <nikita.yoush@cogentembedded.com> | 2021-12-25 22:39:57 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-01-24 09:55:14 +0100 |
| commit | d843e61e0ea50ecf2fc9276c828ea3867867fd89 (patch) | |
| tree | d787424c7636e9b5c06de84a7e873ffdf7ac15ac /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 59a43fa2487bf8ac67a758c4e653ce3db16f86a9 (diff) | |
clk: renesas: r8a7799[05]: Add MLP clocks
Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.
Similar to other R-Car Gen3 SoC, exact information on the parents of MLP
clocks on E3 and D3 is not available. However, since the parents of
these clocks are not anyhow software-controllable, the only harm from
this is inexact information exported via debugfs. So just keep the
parent set in the same way as with other Gen3 SoCs.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions