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| author | Madhav Chauhan <[email protected]> | 2018-07-05 19:19:38 +0530 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2018-07-06 12:14:16 +0300 |
| commit | d61d1b3bbba1054a7a326c18a3c66f822f9fa338 (patch) | |
| tree | 525ba9aa2f2afcaf6cf3f047a80f70591bdbb744 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 45f09f7adc8a10138b158c5805a4d3b20aac611a (diff) | |
drm/i915/icl: Define AUX lane registers for Port A/B
This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.
v2: Review comments from Jani N:
- Define _ICL_PORT_PCS_DW1_AUX_A for consistency
- Three spaces for bitfield definition.
Signed-off-by: Madhav Chauhan <[email protected]>
Reviewed-by: Jani Nikula <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions