diff options
| author | Duc Dang <[email protected]> | 2016-12-01 18:27:07 -0800 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2016-12-06 13:45:50 -0600 |
| commit | c5d4603961009c39de94725213d8b5420f110f9e (patch) | |
| tree | 28d5b46fed39d45cd2b7a28c8c73f161527902bd /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 648d93fc77da4f655cf13108417f33c91d745e2c (diff) | |
PCI: Add MCFG quirks for X-Gene host controller
PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to
configure additional controller's register to address device at
bus:dev:function.
Add a quirk to discover controller MMIO register space and configure
controller registers to select and address the target secondary device.
The quirk will only be applied for X-Gene PCIe MCFG table with
OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
Tested-by: Jon Masters <[email protected]>
Signed-off-by: Duc Dang <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions