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| author | Anshuman Khandual <anshuman.khandual@arm.com> | 2021-08-10 09:59:42 +0530 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2021-08-11 15:33:46 +0100 |
| commit | b31578f627177bda5c16894e3170a7a6a1236136 (patch) | |
| tree | c1385a569e4763753439cd3bf7bdcc2105827c4c /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 6fadc1241c33fe0228c94bc6a1aa6c1da8872e8b (diff) | |
arm64/mm: Define ID_AA64MMFR0_TGRAN_2_SHIFT
Streamline the Stage-2 TGRAN value extraction from ID_AA64MMFR0 register by
adding a page size agnostic ID_AA64MMFR0_TGRAN_2_SHIFT. This is similar to
the existing Stage-1 TGRAN shift i.e ID_AA64MMFR0_TGRAN_SHIFT.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Acked-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1628569782-30213-1-git-send-email-anshuman.khandual@arm.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions