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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-05-30 18:38:48 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-06-11 09:46:19 +0200 |
| commit | a3a632ed87f0913779092c30bd0ea7dfd81601f3 (patch) | |
| tree | d027c1477b6b7b43bb32cb89a3ae14d81408b7f1 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 08b68ae5a0276f293c8da602f963f6de68b3599b (diff) | |
pinctrl: renesas: rzg2l: Validate power registers for SD and ETH
On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
resulting in invalid register offsets. Ensure that the register offsets
are valid before any read/write operations are performed. If the power
registers are not available, both SD and ETH will be set to '0'.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions