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| author | Liu Peibao <[email protected]> | 2024-11-01 16:12:43 +0800 |
|---|---|---|
| committer | Andi Shyti <[email protected]> | 2024-11-08 19:13:06 +0100 |
| commit | 8de3e97f3d3d62cd9f3067f073e8ac93261597db (patch) | |
| tree | 2ba8b90ca7c43aeaaff423109b57e14ea1a1970e /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | ab2e5c8ff253ff612f7c6ef9441d2ff6558e5449 (diff) | |
i2c: designware: do not hold SCL low when I2C_DYNAMIC_TAR_UPDATE is not set
When the Tx FIFO is empty and the last command has no STOP bit
set, the master holds SCL low. If I2C_DYNAMIC_TAR_UPDATE is not
set, BIT(13) MST_ON_HOLD of IC_RAW_INTR_STAT is not enabled,
causing the __i2c_dw_disable() timeout. This is quite similar to
commit 2409205acd3c ("i2c: designware: fix __i2c_dw_disable() in
case master is holding SCL low"). Also check BIT(7)
MST_HOLD_TX_FIFO_EMPTY in IC_STATUS, which is available when
IC_STAT_FOR_CLK_STRETCH is set.
Fixes: 2409205acd3c ("i2c: designware: fix __i2c_dw_disable() in case master is holding SCL low")
Co-developed-by: Xiaowu Ding <[email protected]>
Signed-off-by: Xiaowu Ding <[email protected]>
Co-developed-by: Angus Chen <[email protected]>
Signed-off-by: Angus Chen <[email protected]>
Signed-off-by: Liu Peibao <[email protected]>
Acked-by: Jarkko Nikula <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions