diff options
| author | Peter Zijlstra <[email protected]> | 2017-04-13 14:56:44 +0200 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2017-05-15 10:15:14 +0200 |
| commit | 8309f86cd41e8714526867177facf7a316d9be53 (patch) | |
| tree | ea2ca294166540ec796bfcdb8c3936aabfd61fa9 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 625ed2bf049d5a352c1bcca962d6e133454eaaff (diff) | |
x86/tsc: Provide 'tsc=unstable' boot parameter
Since the clocksource watchdog will only detect broken TSC after the
fact, all TSC based clocks will likely have observed non-continuous
values before/when switching away from TSC.
Therefore only thing to fully avoid random clock movement when your
BIOS randomly mucks with TSC values from SMI handlers is reporting the
TSC as unstable at boot.
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Mike Galbraith <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions