ARM: Add Krait L2 register accessor functions

Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write.  Then you
read/write the 'window' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.

Cc: Mark Rutland <[email protected]>
Cc: Russell King <[email protected]>
Acked-by: Bjorn Andersson <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Tested-by: Craig Tatlor <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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