diff options
| author | Chanho Park <[email protected]> | 2022-07-29 09:30:23 +0900 |
|---|---|---|
| committer | Krzysztof Kozlowski <[email protected]> | 2022-08-23 09:21:35 +0300 |
| commit | 3477b3c3a9fbb6422874c7f24a35249e1773c687 (patch) | |
| tree | b569da36e6e5d19817c5937ac2e34e76747fbc82 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 67d98943408bce835185688cb75ebbb45b91e572 (diff) | |
clk: samsung: exynosautov9: add fsys0 clock support
CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
Lanes.
Signed-off-by: Chanho Park <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/ae84d4a0487a5299076bfeef5732579f5207acf9.1659054220.git.chanho61.park@samsung.com
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions