diff options
| author | Christophe Roullier <[email protected]> | 2020-04-27 12:00:38 +0200 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2020-05-01 15:17:32 -0700 |
| commit | 1bb694e208395816fee278ca46d2796727d3f4a9 (patch) | |
| tree | 3346687f5b3bcbf30ba8cc414f0fcc7a55809fa5 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | f0628c524fd188c3f9418e12478dfdfadacba815 (diff) | |
net: ethernet: stmmac: simplify phy modes management for stm32
No new feature, just to simplify stm32 part to be easier to use.
Add by default all Ethernet clocks in DT, and activate or not in function
of phy mode, clock frequency, if property "st,ext-phyclk" is set or not.
Keep backward compatibility
--------------------------------------------------------------------------
|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal | No 125Mhz |
| | | 25MHz | 50MHz | from PHY |
--------------------------------------------------------------------------
| MII | - | eth-ck | n/a | n/a |
| | | st,ext-phyclk | | |
--------------------------------------------------------------------------
| GMII | - | eth-ck | n/a | n/a |
| | | st,ext-phyclk | | |
--------------------------------------------------------------------------
| RGMII | - | eth-ck | n/a | eth-ck |
| | | st,ext-phyclk | |st,eth-clk-sel|
| | | | | or |
| | | | | st,ext-phyclk|
----------------==--------------------------------------------------------
| RMII | - | eth-ck | eth-ck | n/a |
| | | st,ext-phyclk | st,eth-ref-clk-sel | |
| | | | or st,ext-phyclk | |
--------------------------------------------------------------------------
Signed-off-by: Christophe Roullier <[email protected]>
Acked-by: Alexandre TORGUE <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions