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| author | Suneel Garapati <[email protected]> | 2024-04-23 00:46:04 -0700 |
|---|---|---|
| committer | Andi Shyti <[email protected]> | 2024-05-06 00:56:38 +0200 |
| commit | 114c69f4be3f3a55355b2f1db46a820bb0364457 (patch) | |
| tree | 1771e87edf114494ec53d54a0e036ea6911513b2 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | 29914dac94d490001bdfc5b9fdb8a5c29a724c1b (diff) | |
i2c: thunderx: Clock divisor logic changes
Handle changes to clock divisor logic for OcteonTX2 SoC family using
subsystem ID and using default reference clock source as 100MHz.
Signed-off-by: Suneel Garapati <[email protected]>
Signed-off-by: Piyush Malgujar <[email protected]>
Acked-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions