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| author | Rohit Agarwal <[email protected]> | 2022-02-22 10:26:23 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2022-04-12 21:22:26 -0500 |
| commit | 02c5553523c6cfdab4335ab26ff65f679c7c91ac (patch) | |
| tree | f9bee50becb3c19c8ddf555fa729a1fe83dda8f3 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | c20aa951ee14fe0dfa2beed19aaee1fd33d50a6e (diff) | |
ARM: dts: qcom: sdx65: Add support for A7 PLL clock
On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.
Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions