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authorWill Deacon <[email protected]>2018-08-23 21:16:50 +0100
committerCatalin Marinas <[email protected]>2018-09-11 16:49:12 +0100
commitace8cb754539077ed75f3f15b77b2b51b5b7a431 (patch)
treebab41795267bc907a837e48799405ee489672604 /tools/perf/scripts/python/stat-cpi.py
parentf270ab88fdf205be1a7a46ccb61f4a343be543a2 (diff)
arm64: tlb: Avoid synchronous TLBIs when freeing page tables
By selecting HAVE_RCU_TABLE_INVALIDATE, we can rely on tlb_flush() being called if we fail to batch table pages for freeing. This in turn allows us to postpone walk-cache invalidation until tlb_finish_mmu(), which avoids lots of unnecessary DSBs and means we can shoot down the ASID if the range is large enough. Acked-by: Peter Zijlstra (Intel) <[email protected]> Signed-off-by: Will Deacon <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
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