diff options
| author | Will Deacon <[email protected]> | 2018-08-22 21:40:30 +0100 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2018-09-11 16:49:10 +0100 |
| commit | 45a284bc5ee3d629b6da1498c2273cb22361416e (patch) | |
| tree | bc6dd47bd4a105654b6fd8821e513cf22b7e698e /tools/perf/scripts/python/stat-cpi.py | |
| parent | 6899a4c82faf9b41bbddf330651a4d1155f8b64e (diff) | |
arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()
__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.
In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.
Acked-by: Peter Zijlstra (Intel) <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stat-cpi.py')
0 files changed, 0 insertions, 0 deletions