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authorAmit Cohen <[email protected]>2022-06-19 13:29:18 +0300
committerDavid S. Miller <[email protected]>2022-06-20 10:03:33 +0100
commit27f0b6ce06d7a919f05c3a21e47249278f2b33c0 (patch)
tree210a868446b22fd52b1492ce4e6a0db5bd709ed0 /tools/perf/scripts/python/stat-cpi.py
parent48bca94fff12b869c4e124b1201fb908c7c16e29 (diff)
mlxsw: reg: Add Router Egress Interface to VID Register
The REIV maps {egress router interface (eRIF), egress_port} -> {vlan ID}. As preparation for unified bridge model, add REIV register for future use. In the past, firmware would take care of the above mentioned mapping, but in the new model this should be done by software using REIV register. REIV register supports a simultaneous update of 256 ports using 'port_page' field. When 'port_page'=0 the records represent ports 0-255, when 'port_page'=1 the records represent ports 256-511 and so on. The register is reserved while using the legacy model. Signed-off-by: Amit Cohen <[email protected]> Reviewed-by: Petr Machata <[email protected]> Signed-off-by: Ido Schimmel <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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