diff options
| author | Martin Blumenstingl <[email protected]> | 2017-08-05 14:16:24 +0200 |
|---|---|---|
| committer | Boris Brezillon <[email protected]> | 2017-08-23 16:49:21 +0200 |
| commit | fd213b5bae800dc00a2930dcd07f63ab9bbff3f9 (patch) | |
| tree | b194d8f63961a1e79c527b070367bcf8d0632b44 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3bff08dffe3115a25ce04b95ea75f6d868572c60 (diff) | |
mtd: nand: hynix: add support for 20nm NAND chips
According to the datasheet of the H27UCG8T2BTR the NAND Technology field
(6th byte of the "Device Identifier Description", bits 0-2) the
following values are possible:
- 0x0 = 48nm
- 0x1 = 41nm
- 0x2 = 32nm
- 0x3 = 26nm
- 0x4 = 20nm
- (all others are reserved)
Fix this by extending the mask for this field to allow detecting value
0x4 (20nm) as valid NAND technology.
Without this the detection of the ECC requirements fails, because the
code assumes that the device is a 48nm device (0x4 & 0x3 = 0x0) and
aborts with "Invalid ECC requirements" because it cannot map the "ECC
Level". Extending the mask makes the ECC requirement detection code
recognize this chip as <= 26nm and sets up the ECC step size and ECC
strength correctly.
Signed-off-by: Martin Blumenstingl <[email protected]>
Fixes: 78f3482d7480 ("mtd: nand: hynix: Rework NAND ID decoding to extract more information")
Cc: <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions