diff options
| author | Douglas Anderson <[email protected]> | 2019-12-18 14:35:24 -0800 |
|---|---|---|
| committer | Neil Armstrong <[email protected]> | 2020-02-13 10:21:08 +0100 |
| commit | fa8a66c68755ce736053f993e74b2e39df58d2db (patch) | |
| tree | 3d4fb9db55e8893ac46eae353b1be99e7ba95ffe /tools/perf/scripts/python/stackcollapse.py | |
| parent | 2f8fcc7794c147fbb6c0b0e2e4d65876034ff874 (diff) | |
drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link
The ti-sn65dsi86 is a bridge from MIPI to DP and thus has two links:
the MIPI link and the DP link. The two links do not need to have the
same format or number of lanes. Stop using MIPI variables when
talking about the DP link.
This has zero functional change because:
* currently we are hardcoding the MIPI link as unpacked RGB888 which
requires 24 bits and currently we are not changing the DP link rate
from the bridge's default of 8 bits per pixel.
* currently we are hardcoding both the MIPI and DP as being 4 lanes.
This is all in prep for fixing some of the above.
Signed-off-by: Douglas Anderson <[email protected]>
Tested-by: Rob Clark <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/20191218143416.v3.3.Ia6e05f4961adb0d4a0d32ba769dd7781ee8db431@changeid
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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