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authorChen-Yu Tsai <[email protected]>2022-12-01 16:42:27 +0800
committerMatthias Brugger <[email protected]>2023-01-09 17:16:48 +0100
commitf19f68e56b0c6631984a9f5023035d4bd09612bb (patch)
treedaf30a5d048126d6a55128dee11df3c3bd30e3a5 /tools/perf/scripts/python/stackcollapse.py
parentce8a06b5bac75ccce99c0cf91b96b767d64f28a7 (diff)
arm64: dts: mediatek: mt8192: Fix systimer 13 MHz clock description
The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8192 this divider is fixed to /2 and is not configurable. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 48489980e27e ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
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