diff options
| author | Stefan Agner <[email protected]> | 2015-11-17 18:05:25 -0800 |
|---|---|---|
| committer | Stefan Agner <[email protected]> | 2016-02-25 16:13:16 -0800 |
| commit | efb8b49196c0cb0723024182e04072abaec96cdf (patch) | |
| tree | 279c06460c0b24a8edefc58aa34ac609f5721a66 /tools/perf/scripts/python/stackcollapse.py | |
| parent | a36c9867d44718487262643cdefd12a386841b41 (diff) | |
drm/fsl-dcu: specify volatile registers
Since we are using cached registers, we need to specify volatile
registers explicitly to avoid reading their value from the cache.
This allows to read the correct interrupt status in fsl_dcu_drm_irq
and clear the asserted bits only.
Signed-off-by: Stefan Agner <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions