clk: zte: pd_bit is not 0 on zx296718

The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field.  The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.

Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.

Signed-off-by: Shawn Guo <[email protected]>
Reviewed-by: Jun Nie <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

0 files changed, 0 insertions, 0 deletions