diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-06-20 15:57:35 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-01 11:35:08 +0200 |
| commit | ecbc5206a1a0532258144a4703cccf4e70f3fe6c (patch) | |
| tree | e433e891581927e4af018b8bdc08be2536323e4d /tools/perf/scripts/python/stackcollapse.py | |
| parent | 4036bae6dfd782d414040e7d714abc525b2e8792 (diff) | |
arm64: dts: renesas: r9a07g044: Add missing hypervisor virtual timer IRQ
Add the missing fifth interrupt to the device node that represents the
ARM architected timer. While at it, add an interrupt-names property for
clarity,
Fixes: 68a45525297b2e9a ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/21f556eb7e903d5b9f4c96188fd4b6ae0db71856.1718890849.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions