diff options
| author | Stefan Riedmueller <s.riedmueller@phytec.de> | 2021-09-27 09:28:57 +0200 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2021-10-01 10:15:51 +0300 |
| commit | d1012253a2d377f389ea09a82e04b2241fb30b10 (patch) | |
| tree | f8eb8c855b665e7d124150cb784523c3171ad6d4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 2f9d61869640f732599ec36b984c2b5c46067519 (diff) | |
clk: imx: imx6ul: Fix csi clk gate register
According to the imx6ul Reference Manual the csi clk gate register is
CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the
Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the
csi clk gate which is the current setting.
Tests have shown though that the correct csi clk gate register for the
imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct
register for both platforms.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Tested-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210927072857.3940880-2-s.riedmueller@phytec.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions