diff options
| author | Anurag Kumar Vulisha <[email protected]> | 2020-06-29 15:00:52 +0300 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2020-06-29 18:48:00 +0530 |
| commit | cea0f76a483d1270ac6f6513964e3e75193dda48 (patch) | |
| tree | 77f90f9a47a6cdcd08892d317d2d33110846149a /tools/perf/scripts/python/stackcollapse.py | |
| parent | dcbec046507615d7c4b5f6682dc11a1be9a2924c (diff) | |
dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
Signed-off-by: Anurag Kumar Vulisha <[email protected]>
Signed-off-by: Laurent Pinchart <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions