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| author | Yazen Ghannam <yazen.ghannam@amd.com> | 2017-12-04 17:54:38 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2017-12-04 20:38:44 +0100 |
| commit | c8a4364c33ac7ed63278267b8f6d8c15810d5fd1 (patch) | |
| tree | 0b9d85b5d6466c4d0c6e37babf647803e7e6895a /tools/perf/scripts/python/stackcollapse.py | |
| parent | e085ac7a6ddbd746966083c5e13aa290c3e9a253 (diff) | |
x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems
The McaIntrCfg register (MSRC000_0410), previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.
This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.
Only set MSRC000_0410[2:1] on non-SMCA systems.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20171120162646.5210-1-Yazen.Ghannam@amd.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions