diff options
| author | José Roberto de Souza <[email protected]> | 2019-12-22 17:06:51 -0800 |
|---|---|---|
| committer | José Roberto de Souza <[email protected]> | 2019-12-23 09:26:43 -0800 |
| commit | c59053dc58fa3b81ade8e4b411c0e127669c9167 (patch) | |
| tree | 509da92bd88dcaa0fb65f8b770572da143c4565c /tools/perf/scripts/python/stackcollapse.py | |
| parent | 659f14158f1f0d6d8b3246aa67898fd66b0d5cda (diff) | |
drm/i915/dp: Fix MST disable sequence
The disable sequence after wait for transcoder off was not correctly
implemented.
The MST disable sequence is basically the same for HSW, SKL, ICL and
TGL, with just minor changes for TGL.
With this last patch we finally fixed the hotplugs triggered by MST
sinks during the disable/enable sequence, those were causing source
to try to do a link training while it was not ready causing CPU pipe
FIFO underrrus on TGL.
v2: Only unsetting TGL_TRANS_DDI_PORT_MASK for TGL on the post
disable sequence
v4: Rebased, moved MST sequences to intel_mst_post_disable_dp()
BSpec: 4231
BSpec: 4163
BSpec: 22243
BSpec: 49190
Cc: Ville Syrjälä <[email protected]>
Cc: Lucas De Marchi <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]>
Signed-off-by: José Roberto de Souza <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions